Product Details:
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Place of Origin: | original |
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Brand Name: | original |
Certification: | ISO9001:2015standard |
Model Number: | A3P250-PQG208I |
Payment & Shipping Terms:
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Minimum Order Quantity: | 10pcs |
Price: | Contact us to win best offer |
Packaging Details: | Standard |
Delivery Time: | 1-3 workdays |
Payment Terms: | L/C, T/T, Western Union,PayPal |
Supply Ability: | 10000pcs/months |
Detail Information |
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Mounting Style: | SMD/SMT | Package / Case: | PQFP-208 |
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Packaging: | Tray | Number Of Gates: | 250000 |
Product Type: | FPGA - Field Programmable Gate Array | Total Memory: | 36864 Bit |
High Light: | A3P250-PQG208I Programmable Logic ICs,Lead Free Programmable Logic ICs,FPGA Field Programmable Gate Array |
Product Description
A3P250-PQG208I Programmable Logic ICs FPGA Field Programmable Gate Array A3P250-PQG208I LEAD FREE
Features and Benefits
High Capacity
• 15 K to 1 M System Gates
• Up to 144 Kbits of True Dual-Port SRAM
• Up to 300 User I/Os Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
• Instant On Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off High Performance
• 350 MHz System Performance
• 3.3 V, 66 MHz 64-Bit PCI† In-System Programming (ISP) and Security
• ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption (except ARM®-enabled ProASIC®3 devices) via JTAG (IEEE 1532–compliant)† • FlashLock® to Secure FPGA Contents Low Power
• Core Voltage for Low Power
• Support for 1.5 V-Only Systems
• Low-Impedance Flash Switches High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
Advanced I/O
• 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Wide Range Power Supply Voltage Support per JESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6 V
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X† and LVCMOS 2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS (A3P250 and above) • I/O Registers on Input, Output, and Enable Paths • Hot-Swappable and Cold Sparing I/Os‡
• Programmable Output Slew Rate† and Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the ProASIC3 Family Clock Conditioning Circuit (CCC) and PLL†
• Six CCC Blocks, One with an Integrated PLL
• Configurable Phase-Shift, Multiply/Divide, Delay Capabilities and External Feedback
• Wide Input Frequency Range (1.5 MHz to 350 MHz) Embedded Memory†
• 1 Kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations)†
• True Dual-Port SRAM (except ×18) ARM Processor Support in ProASIC3 FPGAs
• M1 ProASIC3 Devices—ARM®Cortex®-M1 Soft Processor Available with or without Debug
Product Category: | FPGA - Field Programmable Gate Array |
A3P250 | |
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151 I/O | |
1.425 V | |
1.575 V | |
- 40 C | |
+ 100 C | |
SMD/SMT | |
PQFP-208 | |
Tray | |
Height: | 3.4 mm |
Length: | 28 mm |
Maximum Operating Frequency: | 350 MHz |
Moisture Sensitive: | Yes |
Number of Gates: | 250000 |
Operating Supply Current: | 30 mA |
Operating Supply Voltage: | 1.5 V |
Product Type: | FPGA - Field Programmable Gate Array |
24 | |
Subcategory: | Programmable Logic ICs |
Total Memory: | 36864 bit |
Width: | 28 mm |
Unit Weight: | 0.669609 oz |
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